## PLCs Training

Class Information
 Tooling U-SME classes are offered at the beginner, intermediate, and advanced levels. The typical class consists of 12 to 25 lessons and will take approximately one hour to complete.
 Class Name: PLC Timers and Counters 260 Description: This class explains how different types of PLC timers and counters work. Difficulty: Intermediate Number of Lessons: 16 Language: English, Spanish

Class Outline
• Objectives
• PLC Timers and Counters
• True and False Values
• How PLC Timers Work
• Timer Accuracy
• Timer Instructions
• Retentive and Nonretentive Timers
• Timer Delay Types
• One Shot
• How PLC Counters Work
• Types of PLC Counters
• Counter Instructions
• Counter Status Bits
• Summary

Class Objectives
• Define the role of PLC timers and counters.
• Describe how true and false values are interpreted by a PLC.
• Describe how PLC timers work.
• Define PLC accuracy.
• Describe PLC timer addressing protocols.
• Describe how PLC timer instructions work.
• Differentiate between retentive and nonretentive timers.
• Differentiate between on delay and off delay timers.
• Describe a one shot.
• Describe how PLC counters work.
• Differentiate between up counters, down counters, and up/down counters.
• Describe how PLC counter instructions work.
• Describe status bits for PLC counters.

Class Vocabulary

Vocabulary TermDefinition
The number of time units or counts that have accrued. When the accumulated value equals the preset value, the done bit is enabled.
A device that keeps track of how much time has passed and remembers this value even if the timer stops timing. An example of an accumulating timer is a stopwatch.
A device that decreases the current value by an increment of 1 every time an input transitions from false to true. Count down counters should always start counting at the preset value.
A counter bit that decreases the current value by an increment of 1 when the bit is true (1). The count down enable bit is only used on down counters.
A counter bit that is set when the accumulated count exceeds -32,768. When the counter reaches this value, it wraps around and starts the next count at +32,767.
A device that increases the current value by an increment of 1 every time an input transitions from FALSE to TRUE. Count up counters are started from zero and continue counting until the accumulated value matches the preset value.
A counter bit that increases the current value by an increment of 1 when the bit is true (1). The count up enable bit is only used on up counters.
A counter bit that is set when the accumulated count exceeds +32,767. When the counter reaches this value, it wraps around and starts the next count at -32,768.
A set of PLC instructions that counts, calculates, or keeps a record of the number of times something happens.
The maximum value the counter can count and register. The count range of the counter is determined by the number of digits the counter is able to display.
A character used to separate different parts of an address. Common delimiter characters are the colon (:) and the period (.).
A bit that ends the time delay or counter count when the accumulated value is equal to the preset value. The done bit is one of the most frequently used status bits.
Counting in a downward or decreasing direction. Counting 3, 2, 1, and so on is a down-count.
The point on an AC signal wave at which change occurs. PLC counters use the rising and falling edge of a signal to count.
A timer or counter instruction that is made up of three 16-bit words that indicate the status and value of the timer or counter.
A bit that begins timer timing when the bit is true (1). The enable bit is one of the most frequently used status bits.
A command on a ladder diagram that tells the PLC to transfer the outputs from the image table and execute the outputs.
A basic PLC logic instruction symbol. Also referred to as Examine If Open.
A basic PLC logic instruction symbol. Also referred to as Examine If Closed.
The point at which an AC signal wave transitions from high to low.
A PLC input contact condition that does not trigger an output--an OFF condition. A false condition exists when the presense or absence of an input does not match the logic of the contact.
A diagram that shows the logic of an electrical circuit or system using standard symbols. The individual lines or "rungs" connected between two vertical lines resemble a ladder.
A type of timer that always starts the time delay from zero. If a nonretentive timer is stopped before the time delay is up, it resets to zero.
A series of ladder instructions that energizes an output for one scan only.
A bit that helps the counter keep track of counts that exceed maximum values allowed by the PLC numbering system.
A device that counts, calculates, or keeps a record of the number of times something happens. PLC counters do not exist in the real world, but rather as a set of instructions inside the PLC microprocessor.
A control device that automatically starts or stops machines and other devices when a preset time period has been exceeded. PLC timers do not exist in the real world, but rather as a set of instructions inside the PLC microprocessor.
A value set in advance that triggers a timer or counter action. When the accumulated value equals the preset value, the done bit is enabled.
An instruction that erases the accumulated time or count and sets the value to zero.
A type of timer that keeps track of how much time has passed and remembers this value even if the timer stops timing. An example of a retentive timer is a stopwatch.
The point at which an AC signal wave transitions from low to high.
The horizontal programming lines in ladder logic. Each rung controls one output.
The condition or state of the PLC timer or counter.
A bit that controls the condition or state of the PLC timer or counter. The two most frequently used status bits are enable (EN) and done (DN).
An element of a timer or counter address that is subordinate or second to the main parts of the timer/counter address.
The unit of measurement used to determine the speed at which time increments are counted. Time base is usually measured in fractions of a second.
A set of PLC instructions that automatically starts or stops machines and other devices when a preset time period has been exceeded.
The degree of difference between the time base and the amount of time it takes to scan the ladder program. If the PLC scan time is too slow, it can cause input/output errors.
An alphanumeric code that specifies the location of the timer in the PLC's memory. The address T4:0 stand for timer file 4, time 0.
A folder in the PLC’s menu system that stores timers.
A delay timer that immediately closes contacts when the control coil is energized, then waits for a predetermined amount of time to open them after power is removed from the coil.
A timer that waits to turn on the output after receiving an on signal from the input.
The bit that stores the accumulated time during the time delay.
A PLC input contact condition that triggers an output--an ON condition. A true condition exists when the presense or absence of an input matches the logic of the contact.
A bit that helps the counter keep track of counts that exceed minimum values allowed by the PLC numbering system.
Counting in an upward or increasing direction. Counting 1, 2, 3, and so on is an up-count.
A combination of up counters and down counters that allows you to increase and decrease values by an increment of 1.
A 16 bit word that stores the time increments and counts of PLC timers and counters.
An instruction that stores the preset value (PRE) of a PLC timer or counter.
An instruction that stores the accumulated value (ACC) of a PLC timer or counter.
An instruction that contains status bits that are used in ladder logic to activate and deactivate PLC timers and counters when certain conditions become true.